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W972GG6JB
9.11.2 AC Characteristics and Operating Condition for -25/25I/25A/25K/-3/-3A speed grades
Notes: 1-3 and 45-47 apply to the entire table
SYM.
SPEED GRADE
Bin(CL-t RCD -t RP)
DDR2-800
( -25/25I/25A/25K )
5-5-5/6-6-6
DDR2-667
( -3/-3A )
5-5-5
UNITS 25 NOTES
PARAMETER
MIN.
MAX.
MIN.
MAX.
t RCD
t RP
t RC
t RAS
t RFC
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Auto Refresh to Active/Auto Refresh command
period
-40°C ≤ T CASE ≤ 85°C*
12.5
12.5
57.5
45
195
?
?
?
?
70000
?
7.8
15
15
60
45
195
?
?
?
?
70000
?
7.8
nS
nS
nS
nS
nS
μ S
23
23
23
4,23
5
5
t REFI
Average periodic
refresh Interval
0°C ≤ T CASE ≤ 85°C
85°C < T CASE ≤ 95°C
95°C < T CASE ≤ 105°C*
?
?
?
7.8
3.9
3.9
?
?
?
7.8
3.9
?
μ S
μ S
μ S
5
5,6
5,6
t CCD
CAS to CAS command delay
2
?
2
?
n CK
t CK(avg) @ CL=3
5
8
5
8
nS
30,31
t CK(avg) Average clock period
t CK(avg) @ CL=4
t CK(avg) @ CL=5
3.75
2.5
8
8
3.75
3
8
8
nS
nS
30,31
30,31
t CK(avg) @ CL=6
t CH(avg) Average clock high pulse width
t CL(avg) Average clock low pulse width
2.5
0.48
0.48
8
0.52
0.52
?
0.48
0.48
?
0.52
0.52
nS
t CK(avg)
t CK(avg)
30,31
30,31
30,31
t AC
DQ output access time from CLK/ CLK
-400
400
-450
450
pS
35
t DQSCK DQS output access time from CLK / CLK
-350
350
-400
400
pS
35
t DQSQ
t CKE
t RRD
t FAW
t WR
t DAL
t WTR
t RTP
DQS-DQ skew for DQS & associated DQ signals
CKE minimum high and low pulse width
Active to active command period for 2KB page size
Four Activate Window for 2KB page size
Write recovery time
Auto-precharge write recovery + precharge time
Internal Write to Read command delay
Internal Read to Precharge command delay
?
3
10
45
15
WR + tn RP
7.5
7.5
200
?
?
?
?
?
?
?
?
3
10
50
15
WR + tn RP
7.5
7.5
240
?
?
?
?
?
?
?
pS
n CK
nS
nS
nS
n CK
nS
nS
13
7
8,23
23
23
24
9,23
4,23
t IS (base) Address and control input setup time
t IH (base) Address and control input hold time
175
250
?
?
200
275
?
?
pS
pS
10,26,
40,42,43
11,26,
40,42,43
t IS (ref)
t IH (ref)
t IPW
t DQSS
t DSS
t DSH
t DQSH
t DQSL
Address and control input setup time
Address and control input hold time
Address and control input pulse width for each input
DQS latching rising transitions to associated clock
edges
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
DQS input high pulse width
DQS input low pulse width
375
375
0.6
-0.25
0.2
0.2
0.35
0.35
?
?
?
0.25
?
?
?
?
400
400
0.6
-0.25
0.2
0.2
0.35
0.35
?
?
?
0.25
?
?
?
?
pS
pS
t CK(avg)
t CK(avg)
t CK(avg)
t CK(avg)
t CK(avg)
t CK(avg)
10,26,
40,42,43
11,26,
40,42,43
28
28
28
* -40°C ≤ T CASE ≤ 85°C is for 25I/25A/25K/-3A grade only, 95°C < T CASE ≤ 105°C is for 25K grade only
Publication Release Date: Nov. 29, 2011
- 45 -
Revision A02
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